The application window is expected to close on 11/23/2024

This is an onsite role and will require working out of the Milpitas/San Jose office location.

Who We Are

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Who You'll Work With

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

What You'll Do

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and drive cross functional and external vendor interactions.

Minimum Qualifications:

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 15 years of experience.
• Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators.
• Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
• Prior experience with Scripting skills: Tcl, Python/Perl.
• Prior experience with full chip DFT architecture, hierarchical testing, and high speed interface testing.

Preferred Qualifications:

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development & EDA interactions - Test Architecture, Methodology and Infrastructure
• Background in Test Static Timing Analysis with Test Constraint signoff ownership.
• Past experience with Post silicon validation using DFT patterns and product engineering
• Have participated in multiple tapeouts and silicon bringup activities.